The present invention is a system for controlling communications among a computer processing unit and a plurality of peripheral devices, which peripheral devices are arrayed in operative connection with a plurality of external buses. Specifically, the present invention provides an internal bus routing controller that generates buffer control signals in order to correctly route all possible transfers between the plurality of buses and the computer processing unit on the internal bus provided.
Prior art designs generally have used variations of a bus-central array for a plurality of external buses. Such a bus-central configuration requires that all transfers cross a central bus, with transceivers operatively attached to the central bus for operative connection of other buses to the computer processing unit through the central bus.
There are significant shortcomings associated with such a bus-central design. Principal among the shortcomings is the unsuitability of such a bus-central design for single-chip integration of a computer processing system such as is contemplated by the present invention.
Further, a bus-central design involves increased board trace lengths for all buses because all buses require additional bus runs to be routed to the central bus. Such additional bus runs, in addition to occupying board space ("real estate", in industry parlance) and thereby mitigating against miniaturization of a computer processing system, also provide a greater susceptibility to noise and a greater propensity for electromagnetic signal generation.
Still further, employment of a bus-central design inherently includes in every bus in the bus array the capacitance presented by the central bus. This relatively large capacitance has the detrimental effect of slowing down signal propagation throughout the entire bus array, thereby mitigating against high-speed operation by any peripheral or other component associated with the bus array.